Receiving apparatus, receiving system using same, and receiving method thereof

ABSTRACT

A receiving apparatus ( 100 ) includes demodulation parts ( 101, 102 ) for receiving the respective one of received signals of broadast systems to output demodulated data and timing clocks synchronized with the respective demodulated data, a clock generating part ( 103 ) for outputting, to an A/V decoder ( 107 ), the two timing clocks from the demodulation parts ( 101, 102 ) as high-rate and low-rate timing clocks and for outputting a control signal for multiplexing the two demodulated data from the demodulation parts ( 101, 102 ), and a multiplexing part ( 104 ) for multiplexing, based on the control signal, the two demodulated data to output the multiplexed data to the A/V decoder ( 107 ). The A/V decoder ( 107 ) receives the multiplexed data and timing clocks from the receiving apparatus ( 100 ) to process the video/audio signals of each broadcast.

The present application is based on International ApplicationPCT/JP2004/017155, filed Nov. 18, 2004, which claims priority toJapanese Patent Application No. 2004-127469, filed Apr. 23, 2004, theentire contents of which are hereby incorporated by reference.

TECHNICAL FIELD

The present invention relates to a receiving apparatus for receiving aplurality of digital broadcastings of different broadcast systems orsame broadcast systems such as a satellite digital broadcasting or aground digital broadcasting, and a receiving system using this receivingapparatus and a receiving method thereof.

BACKGROUND ART

Recently, the digitalization of broadcasts and communications haveprogressed with the advancement of digital transmission technology and asemiconductor integrated technology.

A receiving apparatus and a receiving system which simultaneouslyreceive a plurality of broadcasts have a plurality of demodulation partsfor demodulating a received signal in response to each broadcast system,a multiplexing part for multiplexing demodulated data outputted byrespective demodulation parts, a multiplexed separating part forseparating the demodulated data decoded from the demodulated data to bemultiplexed thereby, and a decoding part for decoding the demodulateddata separated by the multiplexed separating part.

An example of such a digital broadcasting apparatus is shown inJP-A-11-122556.

This well-known digital broadcasting receiver includes a demodulationpart tuned to each broadcast system, a multiplexing part for receivingthe demodulated data by the transport packet and multiplexing thedemodulated data by the transport packet at a rate over a total oftransport packet transmission rates of the respective broadcast systems,and a multiplexed separating part for separating decoded and demodulateddata from the multiplexed demodulated data, so as to simultaneouslyreceive a plurality of broadcast systems.

DISCLOSURE OF THE INVENTION Problem to be Solved by the Invention

However, in a well-known digital broadcasting receiving apparatus, therewas a problem that since a large-sized memory circuit such as a memoryfor delaying respective demodulated data was required and a size of thememory circuit was increased to multiplex the demodulated data outputtedfrom a plurality of multiplexing parts in response to respectivebroadcast system at a rate over a total of transport packet transmissionrates of the respective broadcast systems by the transport packet, thewell-known digital broadcasting receiving apparatus was expensive. Inaddition, in well-known digital broadcasting receiving apparatuses,there was no system for multiplexing the demodulated data.

Consequently, an object of the present invention is to provide aninexpensive receiving apparatus capable of multiplexing two demodulateddata using a small-sized circuit without using a large-sized memory, areceiving system using this receiving apparatus, and a receiving methodthereof.

Means to Solve the Problem

In order to achieve the object, an apparatus includes two demodulationparts that respectively input received signals of respective broadcastsystems and output demodulated data thereof. Timing clocks arerespectively synchronized therewith. A clock generating part receivesthe two timing clocks outputted from the demodulation parts, and outputsthe clocks to an A/V decoder as a high-rate timing clock and a low-ratetiming clock. The clock generating part outputs control signals formultiplexing the two demodulated data outputted from the demodulationparts, and a multiplexing part multiplexes the two demodulated data andoutputs them to the A/V decoder, based on the control signals. The A/Vdecoder processes audio/video signals of respective broadcastings byusing the demodulated data and the timing clocks outputted from thereceiving apparatus as the inputs.

ADVANTAGE OF THE INVENTION

With this configuration, two demodulated data can be multiplexed byadding a small-scale circuit without using a large-scale memory. Thereduction in costs and power consumption can be realized by reducing thescale of the circuit, and timing clocks synchronized with thedemodulated data can be synchronized with a single timing clockincluding higher-rate internal timing clock. Also, a timing restrictionof a dowstream A/V decoder (video signal processing device) can berelaxed. Accordingly, the present invention has an advantage ofconstructing a more inexpensive system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a receiving apparatus in embodiment 1 ofthe present invention.

FIG. 2 is a block diagram of a clock generating part of the receivingapparatus.

FIG. 3 is a block diagram of a rate determination part of the receivingapparatus.

FIG. 4 is a timing diagram showing an operation of the receivingapparatus.

FIG. 5 is a block diagram of a receiving apparatus in embodiment 2 ofthe present invention.

FIG. 6 is a block diagram of a clock generating part of the receivingapparatus.

FIG. 7 is a block diagram of a multiplexing part of the receivingapparatus.

FIG. 8 is a timing diagram showing an operation of the receivingapparatus.

FIG. 9 is a block diagram of a receiving apparatus in embodiment 3 ofthe present invention.

FIG. 10 is a timing diagram showing an operation of the receivingapparatus.

FIG. 11 is a block diagram of a receiving apparatus in embodiment 4 ofthe present invention.

FIG. 12 is a block diagram of a receiving apparatus in embodiment 5 ofthe present invention.

FIG. 13 is a flow chart of a receiving method of the receivingapparatus.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described withreference to the drawings.

Embodiment 1

FIG. 1 is a block diagram of a receiving apparatus in embodiment 1 ofthe present invention.

In FIG. 1, reference numeral 100 indicates a receiving apparatus. Thereceiving apparatus 100 receives two signals A and B of digitalbroadcasting from different broadcast systems or from a same broadcastsystem. The receiving apparatus outputs multiplexed data to multiplexthe outputs of respective demodulated data, and high-rate timing clocksand low-rate timing clocks synchronized with the multiplexed data. Inaddition, reference numeral 107 indicates an A/V decoder (an example ofa video signal processing device). The A/V decoder 107 separates themultiplexed data into two demodulated data for decoding, and uses anyone or both of the two demodulated data so as to process an audio/videosignal of each broadcasting by using the multiplexed data, high-ratetiming clocks and low-rate timing clocks outputted from the receivingapparatus 100 as the inputs.

The receiving apparatus 100 includes a first demodulation part 101 and asecond demodulation part 102, a rate determination part 105, a firstselection part 106, a clock generating part 103, and a multiplexing part104.

The first and second demodulation parts 101 and 102 respectively inputthe two received signals A and B, and output demodulated data D1 and D2to the first selection part 106, and timing clocks T1 and T2respectively synchronized therewith to the selection part 106 and therate determination part 105.

The rate determination part 105 compares the respective rates of the twotiming clocks T1 and T2 outputted from the first and second demodulationparts 101 and 102, determines which clock has the higher rate, andoutputs the determination result to the first selection part 106 as acontrol signal C3.

The first selection part 106 selects either of the timing clocks T1 andT2 as a high-rate timing clock TH to output it to the clock generatingpart 103, and outputs the other one to the clock generating part 103 asthe timing clock TL. The first selection part 106 further selects anyone of the demodulated data D1 and D2 outputted from the first andsecond demodulation parts 101 and 102 as the high-rate demodulation dataDH to output it to the multiplexing part 104, and outputs the other oneto the multiplexing part 104 as the low-rate demodulated data DL basedon a control signal C3 (determination result) outputted from the ratedetermination part 105.

The clock generating part 103 generates timing clocks of the demodulateddata DH and DL (that is, the high-rate timing clock of the high-ratedemodulated data DH and the low-rate timing clock of the low-ratedemodulated data DL) to be multiplexed and output to the A/V decoder107. The clock generating part 103 outputs control signals formultiplexing the two demodulated data DH and DL to the multiplexing part104 by using the high-rate timing clock TH and the low-rate timing clockTL outputted from the first selection part 106 (based on the two timingclocks outputted from the demodulation parts 101 and 102) as the inputs.

The multiplexing part 104 multiplexes the demodulated data DH and DLoutputted from the first selection part 106 byte-by-byte based on thecontrol signals outputted from the clock generating part 103, andoutputs the demodulated data to the A/V decoder 107.

Moreover, the first and second demodulation parts 101 and 102 are thedemodulation parts suitable for the broadcasting systems of therespective received signals A and B.

FIG. 2 shows a circuit configuration more specific than that of theclock generating part 103.

The clock generating part 103 outputs the high-rate timing clock TH tothe A/V decoder 107 as the high-rate timing clock as shown in FIG. 2 byusing the high-rate timing clock TH and the low-rate timing clock TLoutputted from the first selection part 106 as the inputs.

In addition, the clock generating part 103 includes a delaying unit 201,an edge detecting unit 202, a second selection unit 203 and a controlsignal generating unit 204, as shown in FIG. 2.

The delaying unit 201 inputs the low-rate timing clock TL for delayingand outputs the timing clock TLD to the second selection unit 203.

The edge detecting unit 202 detects simultaneous rises of the timingclocks, and outputs a logical value “1” (an example of a second logicalvalue) when the rises are simultaneous and a logical value “0” (anexample of an inverting value of the second logical value) when therises are not simultaneous, to the second selection unit 203 as aselection signal SL by using the high-rate timing clock TH and thelow-rate timing clock TL as the inputs.

The second selection unit 203 inputs the low-rate timing clock TL andthe timing clock TLD outputted from the delaying unit 201 and selectsone of the two timing clocks based on the selection signal SL. In otherwords, the second selection unit 203 selects the timing clock TLDdelayed when the selection signal SL has a logical value “1” and selectsthe low-rate timing clock TL when the selection signal SL has a logicalvalue “0”, and outputs the low-rate timing clock TL to the controlsignal generating unit 204 and the A/V decoder 107 as the low-ratetiming clock.

The control signal generating unit 204 inputs the low-rate timing clockand the high-rate timing clock TH outputted from the second selectionunit 203 and outputs a logical value “1” (an example of a third logicalvalue) when the high-rate timing clock TH rises and a logical value “0”(an example of an inverting value of the third logical value) when thelow-rate timing clock rises. The control signal generating unit 204holds the values when a rise does not exist. The control signalgenerating unit 204 outputs the “1” and “0” signals to the multiplexingpart 104 as the control signal identifying the demodulated data DH andDL selected in the multiplexing part 104.

In addition, FIG. 3 shows a more detailed view of the rate determinationpart 105.

The rate determination part 105 includes a first clock counting unit 301and a second clock counting unit 302, and an identification unit 303, asshown in FIG. 3.

The first and second clock counting units 301 and 302 input the twotiming clocks T1 and T2 respectively outputted from the first and seconddemodulation parts 101 and 102, count respective numbers N1 and N2 ofrises (number of clocks) of the timing clocks T1 and T2, and output therespective initialization signals to the identification unit 303 as thecontrol signals C1 and C2 at a predetermined cycle n, so as toinitialize the timing clocks by the outputting of any one of the controlsignals (initialization signals) C1 and C2.

The identification unit 303 identifies the rate determination result,and outputs “1” (an example of a first logical value) when the controlsignal C1 is inputted to the first selection part 106 in advance orsimultaneously and “0” (an example of the inverting value of the firstlogical value) when the control signal C2 is inputted in advance, as thecontrol signal (identification signal) C3 outputted to the firstselection part 106 by using the control signals C1 and C2 respectivelyoutputted from the first and second clock counting units 301 and 302 asthe inputs.

Moreover, the counting values N1 and N2 of the first and second clockcounting units 301 and 302, and the control signals (initializationsignals) C1 and C2 are outputted as shown in FIG. 3.

Operations of the receiving apparatus configured as above will bedescribed. FIG. 4 is a timing diagram of each part in the receivingapparatus 100 shown in FIG. 1.

The first demodulation part 101 performs a demodulation processingsuitable for the broadcast system, and outputs the timing clock T1 andthe demodulated data D1 (A[1], A[2], A[3], . . . ) synchronizedtherewith. In addition, the second demodulation part 102 performs thedemodulation processing suitable for the broadcast system, and outputsthe timing clock T2 and the demodulated data D2 (B[1], B[2], B[3], . . .) synchronized therewith.

The clock counting units 301 and 302 of the rate determination part 105counts the rises of the timing clocks T1 and T2, and the outputs N1 andN2 of the counting values increase as shown in FIG. 4. In addition,since the predetermined cycle has n, a logical value “1” is outputted asthe control signals (initialization signals) C1 and C2 initializing theclock counting units 301 and 302 when N1 and N2 are the same as n(timing 1 and timing 2 in FIG. 4). Further, both of the clock countingunits 301 and 302 are initialized at the time when the cycle n of anyone of the clock counting units 301 and 302 is in n.

The identification unit 303 of the rate determination part 105identifies which of clocks T1 and T2 has a high-rate output bydetermining which one of control signals C1 and C2 first reaches alogical value “1”. The identification unit 303 then outputs a controlsignal C3 representing the result. In the embodiment 1, “1” is outputtedas control signal C3 when the timing clock T1 is high-rate, that is,when the control signal C1 is received either before or simultaneouslywith C2. A “0” is outputted when the timing clock T2 is high-rate, thatis, when the control signal C2 is received before C1.

The first selection part 106 outputs the timing clocks T1 and T2 as thehigh-rate timing clock TH and the low-rate timing clock TL, respectivelywhen the logical value of the control signal C3 is “1”, and outputs thedemodulated data D1 and D2 as the high-rate demodulate data DH and thelow-rate demodulated data DL, respectively, as shown in FIG. 4. Inaddition, the first selection part 106 operates conversely when thelogical value of the control signal C3 is “0”.

The clock generating part 103 outputs the inputted high-rate timingclock TH to the A/V decoder 107 as the high-rate timing clock withoutchange.

The delaying unit 201 of the clock generating part 103 delays thelow-rate timing clock TL to output the timing clock TLD. The edgedetecting unit 202 compares the timing clocks TH and TL, and outputs alogical value “1” as the selection signal SL when the rises aresimultaneous and a logical value “0” when the rises are notsimultaneous. The second selection unit 203 selects the timing clock TLDdelayed when the selection signal SL has the logical value “1” and thetiming clock TL when the selection signal SL has the logical value “0”,so as to output the selected timing clocks to the A/V decoder as thelow-rate timing clock.

The control signal generating unit 204 of the clock generating part 103outputs a logical value “1” as the control signal outputted to themultiplexing part 104 when the high-rate timing clock rises and alogical value “0” when the low-rate timing clock rises. The controlsignal generating unit 204 holds the values when a rise does not exist.

The multiplexing part 104 selects the high-rate demodulated data DH whenthe control signal outputted from the control signal generating unit 204has a logical value “1” and the low-rate demodulate data DL when thecontrol signal outputted from the control signal generating unit 204 hasa logical value “0”, and generates the multiplexed data from thedemodulated data DH and DL as shown in FIG. 4, so as to output them tothe A/V decoder 107.

As shown above, in embodiment 1, since the two demodulated data D1 andD2 can be multiplexed by adding small-scale circuits without using astoring unit (mass memory) for storing the two demodulated data D1 andD2 outputted by the two demodulation parts 101 and 102, the circuitscale and a cost can be reduced by miniaturizing the receiving apparatus100. In addition, the number of output pins is reduced by the multiplexoutput so as to reduce the cost by reducing the size of the receivingapparatus. Further, a deterioration of jitter performance and anincrement of a response time can be avoided so as to sequentially outputthe demodulated data without accumulating the demodulated data in thememory.

In addition, in embodiment 1, even when the rates of the demodulateddata D1 and D2 are changed or unknown (when the synchronized timingclocks T1 and T2 are changed or unknown), the high-rate timing clock isdetermined by the rate determining clock 105, and any one of the timingclocks T1 and T2 outputted from the demodulation parts 101 and 102 isselected and outputted as the high-rate timing clock TH by the firstselection part 106, based on the determination result. Further, any oneof the demodulated data D1 and D2 outputted from the first and seconddemodulation parts 101 and 102 is outputted as the high-rate demodulateddata DH and the other one is outputted as the low-rate demodulated dataDL. Therefore, the processing in one system including the multiplexingpart 104 and the clock generating part 103 can be performed to reducethe circuit scale.

Further, in embodiment 1, it is possible to easily compare the timingclocks T1 and T2 with the small-scale circuit by using the clockcounting units 301 and 302 as the rate determination part 105.

Besides, in embodiment 1, when the two timing clocks T1 and T2 risesimultaneously, the timing clock TLD delayed by the delaying unit 201 isselected as the low-rate timing clock and the rise of the low-ratetiming clock is delayed, so that the two demodulated data D1 and D2 canbe multiplexed without being easily delayed and the reliability can beimproved by delaying a rise time of the low-rate timing clock.

Moreover, varying the predetermined cycle n by the frequencies of thetiming clocks T1 and T2 improves jitter performance. For example, ageneration part of the initialization signals (control signals C1 andC2) of the clock counting units 301 and 302 can be simplified and thecircuit can be further miniaturized by multiplying the cycle n by 2.

In addition, when the rates of the timing clocks T1 and T2 arepreviously known, the rate determination part 105 and the firstselection part 106 are excluded, so as to further miniaturize thecircuit. Further, when the rates of the timing clocks T1 and T2 can beidentified from outside, the only rate determination part 105 can beomitted from the circuit, so as to miniaturize the circuit.

Further, polarities or the logical values of the control signalsindicated in embodiment 1 are determined as shown above.

Embodiment 2

Hereinafter, a receiving apparatus and a receiving method in embodiment2 of the present invention will be described with reference to FIGS. 5to 8 and FIG. 3. Same reference numerals are given to components same asthose of embodiment 1 in FIGS. 1 and 3.

In embodiment 2, a clock generating part 501 is provided in place of theclock generating part 103 and a multiplexing part 503 is provided inplace of the multiplexing part 104.

The clock generating part 501 of embodiment 2 inputs the counting valuesN1 and N2, the control signals (initialization signals) C1 and C2, andthe control signal (identification signal) C3, inputs the high-ratetiming clock TH from the first selection part 106, and outputs thehigh-rate timing clock TH as the high-rate timing clock, so as togenerate and output a clock having a same average frequency as alow-rate timing clock TL and synchronized with the timing clock TH asthe low-rate timing clock.

In addition, the multiplexing unit 503 of embodiment 2 inputs thehigh-rate demodulated data DH, the low-rate demodulated data DL and thelow-rate timing clock TL from the first selection part 106, inputs thelow-rate timing clock from the clock generating part 501, and selectsthe high-rate demodulated data DH and the low-rate demodulated data DL,based on the inputted low-rate timing clock, so as to generate themultiplexed data in byte-sized increments.

FIG. 6 shows a specific circuit configuration of the clock generatingpart 501.

The clock generating part 501 includes a third selection unit 601, astoring unit 602, a mask signal generating unit 603, a mask unit 604 anda logic inverting circuit 605.

The third selection unit 601 inputs the counting values N1 and N2, andthe control signal C3 from the rate determination part 105, selects thecounting value N1 of the first clock counting unit 301 when the controlsignal C3 has the logical value “1”, that is, the timing clock T1 ishigh-rate and the counting value N2 of the second clock counting unit302 when the control signal C3 has the logical value “0”, that is, thetiming clock T2 is high-rate, and outputs the selected counting valuesto the mask signal generating unit 603 as the counting value NH.

The storing unit 602 inputs the counting values N1 and N2, the controlsignals (initialization signals) C1 and C2, and the control signal C3,stores the counting value N2 outputted from the second clock countingunit 302 connected to the low-rate timing clock T2 as a control value Mwhen the control signal C3 has the logical value “1” (when the timingclock T1 is high-rate) and the counting value N1 outputted from thefirst clock counting unit 301 connected to the low-rate timing clock T1as the control value M when the control signal C3 has the logical value“0”, assuming that the control signals (initialization signals) C1 andC2 are inputted, and outputs the counting values to the mask signalgenerating unit 603.

The mask signal generating unit 603 inputs the counting value NHoutputted from the third selection unit 601 and the control value Moutputted from the storing unit 602, and outputs the logical value “1”(an example of the fourth logical value) to the mask unit 604 when thecounting value NH of the third selection unit 601 as the mask signal isnot larger than the control value M and the logical value “0” (anexample of the inverting value of the fourth logical value) when thecounting value NH of the third selection unit 604 is larger than thecontrol value M to the mask unit 604.

The mask unit 604 inputs the high-rate timing clock TH outputted fromthe first selection part 106 and the mask signal outputted from the masksignal generating unit 603, and outputs the high-rate timing clock TH tothe A/V decoder 107 and the multiplexing unit 503 as the low-rate timingclock when the mask signal has the logical value “1”, and the logicalvalue “L” when the mask signal has the logical value “0”.

The logic inverting circuit 605 logic-inverts the high-rate timing clockTH outputted from the first selection part 106 and outputs the high-ratetiming clock TH to the A/V decoder 107.

FIG. 7 shows a specific circuit configuration of the multiplexing part503.

The multiplexing part 503 includes a FIFO unit 701 and a fourthselection unit 702 as shown in FIG. 7.

The FIFO unit 701 writes the low-rate demodulated data DL inputted fromthe first selection part 106 sequentially according to the timing of thelow-rate timing clock TL inputted from the first selection part 106,reads the low-rate demodulated data DL according to the timing of thelow-rate timing clock outputted from the clock generating part 501, andoutputs the low-rate demodulated data DL to the fourth selection unit702.

The fourth selection unit 702 selects the low-rate demodulated data DLoutputted from the FIFO unit 701 when the low-rate timing clockoutputted from the clock generating part 501 has the logical value “1”and the high-rate demodulated data DH when the low-rate timing clock hasthe logical value “0”, generates the multiplexed data, and outputs themultiplexed data to the A/V decoder 107.

FIG. 8 shows operations of the receiving apparatus configured as shownabove.

The storing unit 602 stores the counting output N2 of the second clockcounting unit 302 connected to the low-rate timing clock T2 as thecontrol value M when the counting output N1 of the counting unit 301 atthe timing 1 or 2 is in the predetermined cycle n. In FIG. 8, m isstored. In addition, the storing unit 602 is updated according to thecontrol signal C1 (initialization timing) of the first clock countingunit 301.

The third selection unit 601 selects the counting value N1 of the firstclock counting unit 301 connected to the high-rate timing clock T1 bythe control signal C3 and outputs the counting value N1 as the countingvalue NH.

The mask signal generating unit 603 compares the counting value NHsynchronized with and varied on the high-rate timing clock T1 outputtedfrom the selection unit 601 with the control value M stored in thestoring unit 602, and outputs the logical value “1” as the mask signalwhen the counting value NH is not larger than the control value M andthe logical value “0” when the counting value NH is larger than thecontrol value M.

The FIFO unit 701 writes the low-rate demodulated data DL at the timingof the low-rate timing clock TL and reads the low-rate demodulated dataDL at the timing of the low-rate timing clock. The output of the FIFOunit 701 is synchronized with the low-rate timing clock and, at a burst,outputted as many as the control value M. The fourth selection unit 702selects the output of the FIFO unit 701 when the low-rate timing clockhas the logical value “1” and the high-rate demodulated data DH when thelow-rate timing clock has the logical value “0”, and outputs themultiplexed data.

As described above, in embodiment 2, the two demodulated data DH and DLoutputted by the two demodulation parts 101 and 102 are synchronized bya timing clock synchronized with the high-rate timing clock, and thetimings of the multiplexed outputs are equally spaced. A signalprocessing for processing the multiplexed outputs can be easilyperformed and an entire configuration of the receiving apparatus can besimplified. Furthermore, since a timing restriction of a latter A/Vdecoder 107 can be relaxed, a cheap A/V decoder can be used and thereceiving apparatus can be inexpensively provided.

Further, in embodiment 2, even though rates of the two demodulated dataDH and DL outputted by the two demodulation parts 101 and 102, and thetwo timing clocks TH and TL synchronized therewith are unknown, the ratedetermination can be performed for selecting.

Moreover, in embodiment 2, even though the storing unit 602 determinesthe control value M by using the counting values N1 and N2, the controlsignals (initialization signals) C1 and C2, and the control signal C3determined by the rate determination part 105, the clock generating part501 includes a third clock counting unit which inputs the high-ratetiming clock TH and the low-rate timing clock TL from the firstselection part 106, and outputs the initialization signals at a cyclewhen the number of clocks of the high-rate timing clock TH is counted,being initialized, and a fourth clock counting unit which counts thenumber of clocks of the low-rate timing clock TL, being initialized,whereby the output of the fourth clock counting unit may be stored asthe control value M by the initialization signals of the third clockcounting unit. Then, the mask signal generating unit 603 inputs thecontrol value M of the storing unit 602 and the counting value of thethird clock counting unit, outputs “1” (a fourth logical value) as themask signal when the counting value of the third clock counting unit isnot larger than the control value M and “0” (an inverting value of thefourth logical value) as the mask signal when the counting value of thethird clock counting unit is larger than the control value M. Inaddition, the clock generating part 501 inputs the high-rate timingclock TH and the low-rate timing clock TL from the selection part 106,generates a high-rate timing clock having the same average frequency asthe low-rate timing clock TL, and outputs the high-rate timing clock andthe low-rate timing clock.

Embodiment 3

Hereinafter, a receiving apparatus in embodiment 3 of the presentinvention will be described with reference to the drawings. Moreover,same reference numerals are given to components same as those ofembodiment shown in FIG. 1 and the description thereof will be omitted.

FIG. 9 is a block diagram of the receiving apparatus in embodiment 3 ofthe present invention.

A receiving apparatus 100 includes demodulation parts 101 and 102, afirst data extension part 901 and a second data extension part 902, acontrol signal generating part 903, a multiplexing part 904, a firstclock generating part 905, and a second clock generating part 906.

The first and second data extension parts 901 and 902 input demodulateddata D1 and D2, and timing clocks T1 and T2 respectively synchronizedwith the demodulated data D1 and D2, respectively outputs the timingclocks T1 and T2 alternatively, and split and output the timing clock T1and T2 into T1 a, T1 b, T2 a and T2 b. Furthermore, the first and seconddata extension parts 901 and 902 latches the demodulated data D1synchronized at the respective rises of the timing clocks T1 a and T1 b,generates the demodulated data D1 a and D1 b respectively synchronizedwith the timing clocks T1 a and T1 b, and latches the demodulated D2 atthe respective rises of the timing clocks T2 a and T2 b and generatesand outputs the demodulated data D2 a and D2 b respectively synchronizedwith the timing clocks T2 a and T2 b. That is, two systems includingodd-time timing clocks and odd-time demodulated data synchronizedtherewith, and even-time timing clocks and even-time demodulated dataare respectively outputted.

The control signal generating part 903 inputs a control timing clock Tphaving a cycle T shorter than the shortest cycle of the timing clocks T1and T2, and four demodulated timing clocks (timing clocks T1 a, T1 b, T2a and T2 b) outputted from the first and second data extension parts 901and 902, detects rises of the four demodulated timing clocks by usingthe control timing clock Tp, and outputs the data control signals (T1 a,T1 b, T2 a and T2 b; identification control signals) for identifying thetiming clock detecting the rise at a next control timing clock cycleT(N+1) sequentially and when the rise is detected within the controltiming clock cycle T(N), and holds and outputs the data control signalwhen the rise is not detected.

The multiplexing part 904 selects demodulated data D1 a, D1 b, D2 a andD2 b synchronized with the data control signals, which are outputtedfrom the data extension parts 901 and 902, based on the data controlsignals (T1 a, T1 b, T2 a or T2 b) outputted from the control signalgenerating part 903, generates the multiplexed data, and outputs themultiplexed data to the A/V decoder 107.

The clock generating part 905 inputs the timing clock Tp, and the timingclocks T1 a and T1 b outputted from the first data extension part 901,detects the rises of the timing clocks T1 a and T1 b at the cycle of thecontrol timing clock by using the control timing clock Tp, generates afirst multiplexed timing clock Ta having the rise during the datacontrol signal is outputted within the next cycle T[N+1] when any riseis detected within the control timing clock cycle T[N], and outputs thefirst multiplexed timing clock Ta to the A/V decoder 107.

The clock generating part 906 inputs the control timing clock Tp, andthe timing clocks T2 a and T2 b outputted from the second data extensionpart 902, detects the rises of the timing clocks T2 a and T2 b at thecycle of the control timing clock by using the control timing clock Tp,generates a first multiplexed timing clock Tb having the rise during thedata control signal is outputted within the next cycle T [N+1] when anyrise is detected within the control timing clock cycle T[N], and outputsthe second multiplexed timing clock Ta to the A/V decoder 107.

FIG. 10 shows operations of the receiving apparatus configured asdescribed above.

The first data extension part 901 outputs the timing clock T1alternatively by a cycle, and split and output the timing clock T1 intothe timing clocks T1 a and T1 b. In addition, the first data extensionpart 901 latches the demodulated data D1 synchronized with therespective rises of the timing clocks T1 a and T1 b, and generates thedemodulated data D1 a and D1 b respectively synchronized with the timingclocks T1 a and T1 b. Further, the second data extension part 902outputs the timing clocks T2 a and T2 b, and the demodulated data D2 aand D2 b respectively synchronized with the timing clocks T2 a and T2 b.

The control signal generating part 903 detects the rises of the fourdemodulated timing clocks (timing clocks T1 a, T1 b, T2 a and T2 b) byusing the control timing clock Tp having a cycle shorter than theshortest cycle of the timing clocks T1 and T2. The control signalgenerating part 903 sequentially outputs the data control signals foridentifying the timing clocks of which rises are detected at the nextcycle T[N+1] when the rises are detected within a control timing clockcycle T[N] and holds and outputs the data control signals when the risesare not detected.

In FIG. 10, since the timing clocks T1 a and T2 a rise at the cycleT[1], the data control signal sequentially outputs T1 a and T2 a at thecycle T[2]. Since the timing clocks T1 a and T2 b rise at the cycleT[3], the data control signal sequentially outputs T1 a and T2 b at thecycle T[4]. Since no timing clock rises at the cycle T[4], the datacontrol signal holds the prior T2 b.

The multiplexing part 904 selects the demodulated data D1 a, D1 b, D2 aand D2 b by the data control signal to generate and output themultiplexed data. In FIG. 10, the data control signal having the cycleT[2] represents T1 a and T2 a, the contents AO and BO corresponding toD1 a and D2 a, respectively, are outputted as the multiplexed data.

The first clock generating part 905 detects the rises of the timingclocks T1 a and T2 b at the control timing clock cycle T, and generatesand outputs the first multiplexed timing clock Ta having the rise duringthe output period of the data control signal within the next cycleT[N+1] when detecting the rise of any one within the control timingclock cycle T[N].

The second clock generating part 906 also detects the rises of thetiming clocks T2 a and T2 b at the control timing clock cycle T[N]similarly to the first clock generating part 905, and generates andoutputs the second multiplexed timing clock Tb at the next cycle T[N+1].

As described above, in embodiment 3, by using the control timing clockTp higher-rate than the timing clocks T1 and T2 to extend the datawithout detecting the rates of the first and second demodulated data D1and D2, since the two demodulated data D1 and D2 which operateasynchronously can be easily used with the multiplexed data synchronizedwith a single clock, the scale of the circuit and the number of thedesign processes can be reduced.

Moreover, the control timing clock cycle T is 1/m (m=counting numbers≧2) of the timing clock T1 or T2, whereby the synchronous design can beperformed, the improvement of the design efficiency can be furtherplanned.

In addition, it is preferable that the data extending parts 901 and 902holds the demodulated data at the rises or falls of the timing clocks T1and T2.

Embodiment 4

Hereinafter, a receiving apparatus in embodiment 4 of the presentinvention will be described with reference to FIG. 11. Moreover, in FIG.11, same reference numerals, and a and b for identifying two systemswill be given to components same as those in FIG. 1, and the descriptionthereof will be omitted.

The receiving apparatus in embodiment 4 of the present inventionreceiving 4n-type received signals (n=positive integer ≧1; differentreceived signals A, B, C and D in four broad systems in FIG. 11)comprises 2n rows of receiving apparatuses 100 (such as in embodiment 1)(2n rows in FIG. 11) and generates 4n-type timing clock and 2n-typemultiplexed data to output the 4n-type timing clock and 2n-typemultiplexed data to the A/V decoder 107. Moreover, the receivingapparatus the demodulation parts are suitable for the broadcast systemsof the respective received signals.

As described above, in embodiment 4, when the 4n-type received signalreceived, 2n receiving apparatuses indicated in embodiment 1 arearranged in parallel so as to output the 4n-type received signal as the2n-type multiplexed data. In addition, the two demodulated data can bemultiplexed without using a large-scale memory, the design can be easilyperformed and increment of the board dimension can be prevented so as toprovide the receiving apparatus inexpensively.

Moreover, the receiving apparatus in embodiment 4 has the configurationof the receiving apparatus described in embodiment 1, but may have theconfiguration of the receiving apparatus in embodiment 2 or 3.

In addition, two demodulation parts are configured as the demodulationpart, but the demodulation parts of the respective broadcast systems maybe configured.

Further, the different received signals A, B, C and D of the fourbroadcast systems are adopted as the 4n-type received signal, but thereceived signals of all the same broadcast systems or of the broadcastsystem mixing a same broadcast system and a different broadcast systemmay be adopted as the 4n-type received signal.

Embodiment 5

Hereinafter, a receiving method in embodiment 5 of the present inventionwill be described with reference to FIGS. 12 and 13.

FIG. 12 is a block diagram of a processor which executes the receivingmethod of embodiment 5.

In FIG. 12, reference numerals 1201 and 1202 are an input I/F forinputting received signals A and B of the respective broadcast systems.Reference numeral 1203 is a general built-in memory. In addition,reference numeral 1204 is a CPU for performing the control and theoperation, and reference numeral 1205 is a ROM for storing a controlprogram. Further, reference numeral 1207 is an output I/F for outputtingthe demodulated data multiplexing the demodulated data demodulating therespective received signals and the timing clocks respectivelysynchronized with the demodulated to be multiplexed to the A/V decoder107. A CPU 1204, a ROM 1205 and an output IF 1207 are connected to theinput I/Fs 1201 and 1202 via the built-in memory 1203.

The receiving method by the CPU 1204 is described according to a flowcart of FIG. 13. The CPU 1204 may comprise the components shown in FIG.1, for example, and the signals of embodiment 1, as shown in FIG. 1, arereferenced below referring to FIG. 13.

Step-S1 (Demodulating Step)

First of all, respective received signals A and B are demodulated, basedon respective broadcast systems, and respective demodulated data D1 andD2 are generated in a byte so as to generate the timing clocks T1 and T2synchronized therewith.

Step-S2 (Rate Determining Step)

Next, rates of the two timing clocks T1 and T2 generated in step S1 aredetermined, and the two timing clocks T1 and T2 are outputted as ahigh-rate timing clock TH and a low-rate timing clock TL. In addition,the two demodulated data D1 and D2 generated in step S1 are outputted ashigh-rate demodulated data DH and low-rate demodulated data DLsynchronized with the high-rate timing clock TH and the low-rate timingclock TL.

Step-S3 (Clock Generating Step)

Next, a low-rate timing clock having an average frequency same as thelow-rate timing clock TL is generated by being synchronized withhigh-rate timing clock TH.

More specifically, the clock generating step S3 is configured by stepsS4 to S6 described below.

Step-S4 (Storing Step)

A counting value of the low-rate timing clock TL counted at everypredetermined cycle n of the high-rate timing clock TH is stored as acontrol value M.

Step-S5 (Mask Signal Generation Processing Step)

Next, when the counting value of the high-rate timing clock TH is notlarger than the control value M, a logical value “1” is outputted andthe counting value is larger than the control value M, a logical value“0” is outputted.

Step-S6 (Mask Processing Step)

Next, when a mask signal outputted from step-S5 has a logical value “1”,the high-rate timing clock TH is outputted and the mask signal has alogical value “0”, a logical value “L” is outputted as the low-ratetiming clock.

Step-S7 (Multiplex Processing Step)

Following the clock generating step S3 (S4 to S6), when the low-ratetiming clock has a logical value “1”, the low-rate demodulated data DLare selected and outputted, and when the low-rate timing clock has alogical value “0”, the high-rate demodulated data DH are selected andoutputted.

As described above, in embodiment 5, since the two demodulated data D1and D2 can be multiplexed in a byte by means of the configuration of thegeneral processor, the capacity of the general memory 1203 can belargely reduced, lowering a cost of the receiving apparatus can berealized and the timing clock outputted to the A/V decoder issynchronized with the high-rate timing clock, and the timing restrictionof the connected A/V decoder 107 is relaxed, a cost of a whole systemcan be reduced by using an inexpensive components. In addition, evethough rates of the two demodulated data D1 and D2 outputted by thedemodulation processing, and the two timing clocks T1 and T2synchronized therewith are not known, the two demodulated data D1 and D2can be multiplexed.

INDUSTRIAL APPLICABILITY

In a receiving apparatus of the present invention, two demodulated datacan be multiplexed by adding a small-scale circuit without a large-scalememory, thus a cost reduction by the reduction of the circuit scale andlow power consumption can be realized by the reduction of the circuitscale. A timing clock synchronized demodulated data to be multiplexedcan be synchronized with high-rate timing clock or a signal timing clocksuch as a high-rate timing clock, timing restriction of a latter A/Vdecoder can be relaxed. Thus, a more inexpensive system can beconstructed. Consequently, the receiving apparatus can be applied to asystem which receives a plurality of broadcast systems at one site in aremote place and widely transmits the received data.

1. A receiving apparatus for receiving two digital broadcast signalsfrom different broadcast systems or a single broadcast system, thereceiving apparatus comprising: a first demodulation part and a seconddemodulation part for receiving two such digital broadcast signals,respectively, and for outputting two demodulated data and timing clocksignals respectively synchronized with two such demodulated data; aclock signal generating part based on said two timing clock signalsoutputted from the first and second demodulation parts, for generatingand outputting such respective timing signals of two such demodulateddata and for outputting control signals for multiplexing two suchdemodulated data; and a multiplexing part for multiplexing by a byte twosuch demodulated data outputted from the first and second demodulationparts, based on such control signals outputted from the clock signalgenerating part.
 2. A receiving apparatus for receiving two digitalbroadcast signals from different broadcast systems or a single broadcastsystem, the receiving apparatus comprising: a first demodulation partand a second demodulation part for receiving two such digital broadcastsignals, respectively, and for outputting two demodulated data andtiming clock signals respectively synchronized with two such demodulateddata; a clock signal generating part based on said two timing clocksignals outputted from the first and second demodulation parts, forgenerating and outputting such respective timing signals of two suchdemodulated data and for outputting control signals for multiplexing twosuch demodulated data and for outputting control signals formultiplexing two such demodulated data; a multiplexing part formultiplexing by a byte two such demodulated data outputted from thefirst and second demodulation parts, based on such control signalsoutputted from the clock signal generating part; and a first selectionpart for receiving from the first and second demodulation parts two suchtiming clock signals and two such demodulated data, and for selectingand outputting high-rate timing signals and high-rate demodulated datasynchronized therewith, and low-rate timing signals and low-ratedemodulated data synchronized therewith, alternatively from two suchtiming signals and two demodulated data outputted from the first andsecond demodulation parts.
 3. The receiving apparatus according to claim2, further comprising: a rate determination part for comparingrespective rates of such timing clock signals outputted from the firstand second demodulation parts, for determining which clock signal has ahigher rate, and for outputting a control signal to the first selectionpart based on such determination.
 4. The receiving apparatus accordingto claim 3, wherein the rate determination part includes: a first clockcounting unit and a second clock counting unit for counting a respectivenumber of clocks of two such timing clock signals outputted from thefirst and second demodulation parts, and for outputting first and secondinitialization signals, respectively, at a predetermined cycle, each ofthe first clock counting unit and the second clock counting unit beinginitialized by the outputting of such first or second initializationsignal, respectively; and an identification unit for receiving suchfirst and second initialization signals respectively outputted from thefirst and second clock counting units, and for outputting as a controlsignal to the first selection part, a first logical value when an outputof such first initialization signal is received before or simultaneouslywith such second initialization signal, and for outputting an oppositevalue of the first logical value when such second initialization signalis received before such first initialization signal.
 5. The receivingapparatus according to claim 2, wherein the clock signal generating partincludes: an edge detecting unit for receiving and outputting ahigh-rate timing clock signal outputted from the first selection part,for detecting simultaneous rises of a high-rate timing clock signal anda low-rate timing clock signal outputted from the first selection part,and for outputting a second logical value when rises of a high-ratetiming clock signal and a low-rate timing clock signal are simultaneous,and an opposite value of the second logical value when such rises arenot simultaneous as a selection signal; a delaying unit for receiving alow-rate timing clock signal from the first selection part, and foroutputting a delayed low-rate timing clock signal; a second selectionunit that for receiving a low-rate timing clock signal outputted fromthe first selection part and a delayed low-rate timing clock signaldelayed by the delaying unit, for selecting as an output such low-ratetiming clock signal delayed by the delaying unit when the selectionsignal from the edge detecting unit has the second logical value, andfor selecting as an output a low-rate timing clock signal outputted fromthe first selection part when the selection signal from the edgedetecting unit has the opposite value of the second logical value; and acontrol signal generating unit for receiving a high-rate timing clocksignal and a low-rate timing clock signal outputted from the secondselection unit, for outputting to the multiplexing part as a controlsignal for multiplexing two demodulated data a third logical value whena high-rate timing clock signal rises, for outputting as a controlsignal an opposite value of the third logical value when a low-ratetiming clock signal rises, and for holding an output value when a risedoes not occur on either of a high-rate timing clock signal or alow-rate timing clock signal.
 6. A receiving apparatus for receiving twodigital broadcasting signals from different broadcast systems or from asingle broadcasting system, the receiving apparatus comprising: a firstdemodulating part and a second demodulating part for respectivelyreceiving two such digital broadcasting signals, and for outputtingdemodulated data thereof and timing clock signals respectivelysynchronized with such demodulated data, one of such timing clocksignals being a first low-rate timing clock signal and another of suchtiming clock signals being a first high-rate timing clock signal; aclock signal generating part for outputting a second high-rate timingclock signal corresponding to a first high-rate timing clock signaloutputted from the first and second demodulation parts and a secondlow-rate timing clock signal having a same average frequency as a firstlow-rate timing clock signal outputted from the first and seconddemodulation parts, a second low-rate timing clock signal beingsynchronized with the second high-rate timing clock signal; and amultiplexing part that multiplexes, by a byte, demodulated dataoutputted from the first and second demodulation parts, based on saidsecond low-rate timing clock signal outputted from the clock generatingpart.
 7. A receiving apparatus for receiving two digital broadcastingsignals from different broadcast systems or from a single broadcastingsystem, the receiving apparatus comprising: a first demodulating partand a second demodulating part for respectively receiving two suchdigital broadcasting signals, and for outputting demodulated datathereof and timing clock signals respectively synchronized with suchdemodulated data, one of such timing clock signals being a firstlow-rate timing clock signal and another of such timing clock signalsbeing a first high-rate timing clock signal; a clock signal generatingpart for outputting a second high-rate timing clock signal correspondingto a first high-rate timing clock signal outputted from the first andsecond demodulation parts and a second low-rate timing clock signalhaving a same average frequency as a first low-rate timing clock signaloutputted from the first and second demodulation parts, a secondlow-rate timing clock signal being synchronized with the secondhigh-rate timing clock signal; a multiplexing part that multiplexes, bya byte, demodulated data outputted from the first and seconddemodulation parts, based on said second low-rate timing clock signaloutputted from the clock generating part; a first clock counting partand a second clock counting part, each for counting a respective numberof clock signals of two such timing clock signals outputted from thefirst and second demodulation parts and for outputting a first andsecond counted number, each counted number having a respective countingvalue, and for outputting a first initialization signal and a secondinitialization signal at a predetermined cycle, each of the first andsecond clock counting parts being initialized by the outputting of arespective initialization signal; an identification part for receivingas inputs such first and second initialization signals respectivelyoutputted from the first and second clock counting parts, and foroutputting a control signal with a first logical value when such firstinitialization signal is received before or simultaneously with suchsecond initialization signal, and for outputting a control signal withan opposite value of the first logical value when such secondinitialization signal is received before such first initializationsignal; and a first selection part for receiving such first and seconddemodulated data and first and second timing clock signals, associatedwith such digital broadcast signals, from the first and seconddemodulation parts, and for outputting a first timing clock signal asthe high-rate timing clock signal and first demodulated data as thehigh-rate demodulated data when such control signal has the firstlogical value, and for outputting such second demodulated data as thehigh-rate demodulated data when such control signal has the oppositevalue of the first logical value.
 8. The receiving apparatus accordingto claim 7, wherein the clock signal generating part includes: a thirdselection unit for receiving first and second counting values from thefirst and second clock counting parts, and a control signal from theidentification part, and for outputting a third counting valuecorresponding to a counting value of the first clock counting part whensuch control signal has the first logical value, and corresponding to acounting value of the second clock counting part when such controlsignal has the opposite value of the first logical value; a storing unitfor receiving first and second counting values, first and secondinitialization signals, and a control signal from the identificationpart, and for storing and outputting a counting value of the secondclock counting value as a control value when such control signal has thefirst logical value, and for storing and outputting a control valuecorresponding to the counting value of the first clock counting valuewhen such control signal has the opposite value of the first logicalvalue; a mask signal generating unit for receiving a control value fromthe storing unit and a third counting value from the third selectionunit, and for outputting a mask signal corresponding to a fourth logicalvalue when the third counting value is not larger than the controlvalue, and for outputting such mask signal corresponding to an oppositevalue of the fourth logical value when the counting value of the thirdselection unit is larger than the control value; a mask unit forreceiving such mask signal from the mask signal generating unit and ahigh-rate timing clock signal from the selection part, for outputting atiming clock signal corresponding to such high-rate timing clock signalwhen such mask signal has the fourth logical value, and for outputting alogical value “L” low-rate timing clock when the mask signal has theopposite value of the fourth logical value; and a logic invertingcircuit that logic-inverts a high-rate timing clock signal outputtedfrom the first selection part, and outputs a logic-inverted clock signalas a high-rate timing clock signal.
 9. A receiving apparatus forreceiving first and second digital broadcasting signals from differentbroadcast systems or a single broadcast system, the receiving apparatuscomprising: a first demodulation part and a second demodulation part forrespectively receiving first and second digital broadcasting signals,and for outputting demodulated data and timing signals respectivelysynchronized with the demodulated data of such first and second digitalbroadcast signals; a first data extension part for receiving demodulateddata and a timing clock signal from the first demodulation part, and foroutputting first odd-time timing clock signals and first odd-timedemodulated data synchronized therewith, and first even-time timingclock signals and first even-time demodulated data synchronizedtherewith; a second data extension part for receiving demodulated dataand timing clock signals from the second demodulation part, and foroutputting second odd-time timing signals and second odd-timedemodulated data synchronized therewith, and second even-time timingsignals and second even-time demodulated data synchronized therewith; acontrol signal generating part for receiving first and second odd-timetiming clock signals and first and second even-time timing clock signalsfrom the first and second data extension parts, and a control timingclock signal having a cycle not larger than a shortest cycle of all suchtiming clock signals outputted from the first and second demodulationparts, for detecting a rise of first and second odd-time timing clocksignals and first and second even-time timing clock signals from thefirst and second data extension parts within the control timing clockcycle, and for outputting an identification control signal in a nextcycle after a cycle in which a rise is detected; a multiplexing part forselecting, based on an identification control signal outputted from thecontrol signal generating part, demodulated data synchronized with suchidentification control signal and outputted from the first and seconddata extension parts; a first clock signal generating part for receivinga first odd-time timing clock signal, a first even-time timing clocksignal, and a control timing clock signal, for detecting a rise of suchfirst odd-time timing clock or such first even-time timing clock withina control timing clock cycle, and for generating a first multiplexedtiming clock signal having a rising edge within a next cycle of suchidentification control signal; and a second clock signal generating partfor receiving a second odd-time timing clock signal, a second even-timetiming clock signal, and a control timing clock signal, for detecting arise of such second odd-time timing clock signal or such secondeven-time timing clock signal within the control timing clock cycle, andfor generating a second multiplexed timing clock signal having a risingedge within a next cycle of such identification control signal.
 10. Areceiving apparatus comprising 2n (n=positive integer ≧1) units ofreceiving apparatuses according to claim 1 arranged in parallel, whereinthe receiving apparatus inputs 4n-type received signal, and generatesand outputs 4n-type timing clock signals and 2n-type multiplexed data.11. A receiving apparatus comprising: receiving apparatus according toclaim 1; and a video signal processing device that inputs multiplexeddata of two demodulated data outputted from the receiving apparatus andrespective timing clock signals of the multiplexed two demodulated data,and uses at least one of the two demodulated data out of the multiplexeddata as received data.
 12. A method of receiving two digitalbroadcasting signals from different broadcast systems or a singlebroadcast system, the method comprising: providing a receiving apparatuscomprising inputs for receiving digital broadcast signals, at least onememory for storing instructions and data, at least one CPU for executinginstructions, and at least one output; receiving two digitalbroadcasting signals at the inputs of the receiving apparatus;demodulating the two digital broadcasting signals according to thebroadcast system sending the signal; generating demodulated data of eachof the two received signals by a byte; generating two timing clocksignals respectively synchronized with the two digital broadcastingsignals; determining rates of the two generated timing clock signals;outputting two timing clock signals corresponding to the two generatedtiming clock signals, respectively, as a high-rate timing clock signaland a low-rate timing clock signal, and outputting the two generateddemodulated data as high-rate demodulated data and low-rate demodulateddata synchronized with the high-rate timing clock signal and thelow-rate timing clock signal, respectively; storing a counting value ofthe low-rate timing clock signal counted at every predetermined cycle ofthe high-rate timing clock signal as a control value; outputting as amask value a logical value “1” when the counting value of the high-ratetiming clock signal is not larger than the stored control value and alogical value “0” when the counting value is larger than the controlvalue; outputting the high-rate timing clock signal when the mask signalhas a logical value “1”, and the logical value “L” as the low-ratetiming clock signal when the low-rate timing clock signal has a logicalvalue “0”; and selecting and outputting at the output of the receivingapparatus the low-rate demodulated data when the low-rate timing clocksignal has a logical value “1”, and the high-rate demodulated data whenthe low-rate timing clock signal has a logical value “0”.